Designing HPC Architectures at BSC
Join us for our upcoming Future Computing Seminar Series
Speaker: Prof. Miquel Moreto (UPC and BSC)
Date: Wednesday, Jan 14th, 2026, 13:45 CET
Where: ETZ E6
Abstract:
Since 2004, the Barcelona Supercomputing Center is leading the European efforts to develop High Performance Computing (HPC) designs based on domestic technology. In the context of the Mont-Blanc European projects (2011-2021) and in close collaboration with Arm and Atos, BSC deployed the first HPC cluster based on Arm technology. More recently, BSC led the design, verification and fabrication of RISC-V-based vector accelerators in the context of the European Processor Initiative (EPI) and RISC-V general purpose processors in the context of the DRAC project. Since March 2025, BSC is leading the Digital Autonomy with RISC-V in Europe (DARE) project that will develop prototype HPC and AI systems based on EU-designed and developed industry-standard chiplets. In this talk, we will provide an overview of the main achievements in these projects, focusing on the efforts to accelerate HPC workloads with RISC-V official and custom ISA extensions. Finally, we will present current challenges to achieve European technological independence based on the RISC-V open instruction set architecture.
Speaker bio:
Miquel Moreto is an Associate Professor at the Computer Architecture Department at the Universitat Politecnica de Catalunya (UPC). Since 2025, he is the Director of the High Performance Computer Architecture research area at the Barcelona Supercomputing Center (BSC), coordinating 10 research groups and 150 researchers. He received the PhD from the UPC (2010) and was a Fulbright Postdoctoral Fellow at UC Berkeley. During his career, he visited multiple international institutions (IBM, Arm, universities of Cantabria, Edinburgh, and UC Irvine). Since 2018, he is leading the Lagarto initiative that developed the first academic processor in Spain based on the RISC-V ISA.