GAPflow: from NN graph to GAP-optimized C code
Join us for our upcoming Future Computing Seminar Series
Speaker: Marco Fariselli, Greenwaves Technologies
Date: November 12th, 2024, 14:00 CET
Where: ETZ E9 & external page Online
Abstract:
To keep up with the rapidly evolving AI landscape and speed up various machine learning models, modern high-performance MCU devices are equipped with heterogeneous compute units designed to handle different types of workloads, such as CNNs, RNNs, and Transformers, as well as various quantization formats (int8, int16, fp16, etc.). Maximizing the performance of these hardware devices is becoming increasingly challenging from a SW perspective.
In this talk we will present our GAPFlow: the NN compiler that maps computational graphs (such as neural networks) into our target MCU leveraging topology optimizations, mixed precision quantization and optimal memory tiling and allocation.
Bio:
Marco Fariselli received an M.S. in Electronic Engineering from University of Bologna in 2019. Right after that, he joined Greenwaves-Technologies as an Embedded Machine learning Engineer. He is the main developer and maintainer of the internal neural network compilation tools to deploy NN onto Greenwaves chips. Marco also plays a key role in the development of next-generation AI accelerator architectures. During his time at Greenwaves, he has been involved in numerous research projects, both within the company and in collaboration with PhD and Master's students from various research institutions. His primary research interests include embedded AI deployment, mixed-precision quantization, and hardware acceleration for machine learning workloads.