Open and Modular RISC-V Framework for Exploring Energy-Efficient TinyAI Architectures

Join us for our upcoming Future Computing Seminar Series

Speaker: Simone Machetti (EPFL)

Date: Tuesday, Nov 18th, 2025, 10:30 CET

Where: HG D3.2

Abstract:

The rapid expansion of TinyAI applications demands energy-efficient architectures capable of real-time processing within strict power and area constraints. Designing such architectures requires flexible co-design platforms that unify hardware and software development, enabling accurate evaluation of architectural trade-offs while supporting custom accelerators and diverse workloads. Traditional simulators and RTL-based platforms often fall short in balancing speed and accuracy, hindering the exploration of new accelerators and integration schemes. This talk presents an open and modular RISC-V framework that bridges these gaps by enabling rapid prototyping and evaluation of TinyAI architectures, supporting the seamless integration and exploration of custom accelerators. Building on this foundation, the framework is further employed as a case-study environment to investigate the feasibility and trade-offs of adopting general-purpose GPUs at the extreme edge, an approach that has proven highly efficient in other computing domains but remains largely unexplored under the tight TinyAI constraints.

Speaker bio:

Simone Machetti received his M.Sc. degree in Computer Engineering, with a specialization in Embedded Systems, from Politecnico di Torino, Italy. He is currently completing his Ph.D. in Electronic Engineering at the Embedded Systems Laboratory (ESL) of EPFL, Switzerland, where his research focuses on open and modular RISC-V platforms for energy-efficient TinyAI computing. His interests include hardware and software co-design, heterogeneous architectures, and ultra-low-power applications.