Track 2 - Customizing RISC-V Based Microcontrollers

Hands on tutorials to demonstrate how to add your own extensions to an existing 32bit RISC-V microcontroller system, running on an FPGA.

You will learn:

• An introduction to microcontroller architectures (RISC-V, Peripherals, Memories)
• Open source microcontroller architectures available through the PULP eco-system
• FPGA design flow for FPGAs, mapping the RTL code to FPGA
• Getting your code run on the system, cross compiling, RTL simulation, emulation
• Alternatives to expand the capabilities, accelerators, instruction set extensions
• Cost benefit analysis of extensions

Course will be in English with support from UNIBO, ETH Zurich

Nine 2-hour modules with > 50% hands on exercises in computer laboratory.

Limited to 25 participants

Prerequisites: General knowledge on RTL design, basics of computer architectures/programming

Preliminary Agenda:

This Track aims at bringing you up to speed with the development of your own modified flavor of RISC-V based technology – specifically, based on PULPissimo. We focus in particular on the design of extended computation units both inside the core (ISA extensions) and outside it (cooperative or loosely-coupled accelerators), and on delivering all the tools necessary for a productive research environment using PULPissimo as a starting point.

• PULP platform & PULPissimo microcontroller architecture (4h Mon)
  • Lecture: Introduction to the PULPissimo microcontroller architecture
  • Hands-on:
    • Introduction to the PULPissimo simulation environment
    • Plugging an APB timer into the PULPissimo MCU
    • Introduction to the software environment and development of a FIR filter
  • Room: ETZ E8 (morning), ETZ D96.1 (afternoon)
• Extending RISC-V cores and the RISC-V LLVM compiler (6h Tue)
  • Lecture: In-depth RISC-V ISA, microarchitecture of CV32E40X, and CV-XIF specification
  • Hands-on: Extending the RISC-V ISA with new instructions for FIR Filter acceleration
  • Lecture: LLVM RISC-V compiler and its extension
  • Hands-on: Extending LLVM for our FIR instructions, and testing them on the SW FIR filter
  • Room: ETZ D96.1 (all sessions)
    

• Integrating cooperative HW Processing Engines / HWPEs (4h Wed-Thu)
  • Lecture: Why should an ISA extension not be enough? PULP cooperative HWPEs and loosely-coupled accelerators
  • Hands-on:
    • Guided design of a FIR filter HWPE
    • Integration of the FIR HWPE in the PULPissimo architecture
    • Evaluating acceleration in the PULPissimo environment
  • Room: ETZ D96.1 (all sessions)

• Testing extended PULPissimo on FPGA (4h Thu)
  • Lecture: PULPissimo FPGA emulation flow and methodology
  • Hands-on: Deployment flow on FPGA: synthesis + place & route + bitstream generation
  • Hands-on: Testing the design on FPGA with OpenOCD
  • Room: ETZ D96.1 (all sessions)